Electrostatic discharge protection device

ABSTRACT

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, a first and a second doped region formed in the substrate. The first and second doped regions are separated from each other by only the substrate region. The ESD protection device includes no gate above the first and second doped regions. Furthermore, the distance separating the first and second doped regions is defined by a length of a resist during a process of forming the ESD protection device.

[0001] This application is a Divisional of U.S. application Ser. No.09/648,919, filed Aug. 25, 2000 which is incorporated herein byreference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits,and in particular to electrostatic discharge (ESD) devices.

BACKGROUND OF THE INVENTION

[0003] An electrostatic discharge (ESD) event involves a high voltage ora large current inadvertently surging through a conductive path. If thepath includes a pin or an external bonding pad and an internal circuitof an integrated circuit (IC), then the large current of the ESD eventcan surge through the pad and damage the internal circuit and thus theentire IC.

[0004] To protect the IC from damage caused by an ESD event, many ESDprotection devices have been designed. Among them is a snapback-basedESD protection device. Conventionally, there are two types ofsnapback-based ESD protection devices. These two types includefield-oxide NPN and thin-oxide NPN devices. Thin-oxide NPN devices arealso known as NMOS devices. Although the performance of these devices isacceptable, each of them has its problems and limitations.

[0005] In general, problems associated with snapback-based NPNstructures involves junction leakage failures following an ESD event. Inaddition, gate-oxide at the input-buffer can be damaged if the snapbackvoltage of the protection device is too high. The high snapback voltagecan also cause damage to the gate-oxide in the protection device itselffor a thin-oxide NPN device. These issues can lead to undesirable orsubstandard performance of the ESD protection device.

[0006] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foran improved ESD protection device which is less susceptible to failuresseen in the present NPN snapback ESD protection devices.

SUMMARY OF THE INVENTION

[0007] The problems and limitations associated with ESD protectiondevices are addressed by the present invention and will be understood byreading the following disclosure. A novel ESD protection deviceovercomes the problems and limitations of the prior art ESD protectiondevices. The ESD protection device according to the invention is lesssusceptible to failures seen in the present NPN snapback ESD protectiondevices.

[0008] In one aspect, the ESD protection device includes a substrate, afirst doped region formed in the substrate, and a second doped regionformed in the substrate. The first and second doped regions areseparated from each other by only the substrate region. In addition, theESD protection device includes no gate above the first and second dopedregions.

[0009] In another aspect, a method of producing a semiconductor deviceincludes masking a substrate with a resist. Then a first and a seconddoped region are formed in the substrate. The first and second dopedregions are separated by only the substrate, and a spacing between thefirst and second doped regions is defined by a length of the resist.Furthermore, the method includes not forming a gate above the first andsecond doped regions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a prior art thin-oxide NPN ESD protection device.

[0011]FIG. 2A is a prior art field-oxide NPN ESD protection device.

[0012]FIG. 2B is another prior art field-oxide NPN ESD protectiondevice.

[0013]FIG. 3 is an ESD protection device according to the invention.

[0014]FIG. 4 illustrates a p-n junction of the ESD protection device ofFIG. 3.

[0015]FIG. 5 is a current versus voltage graph of the ESD protectiondevice of FIG. 3 during an operating mode.

[0016] FIGS. 6A-C illustrate cross-sectional views of an ESD protectiondevice at various processing stages according to one embodiment of theinvention.

[0017] FIGS. 7A-E illustrate cross-sectional views of an ESD protectiondevice at various processing stages according to another embodiment ofthe invention.

[0018] FIGS. 8A-E illustrate cross-sectional views of an ESD protectiondevice at various processing stages according to another embodiment ofthe invention.

[0019] FIGS. 9A-E illustrate cross-sectional views of an ESD protectiondevice at various processing stages according to another embodiment ofthe invention.

[0020]FIG. 10 is a block diagram of an integrated circuit having the ESDprotection device according to the invention.

[0021]FIG. 11 is a block diagram of a semiconductor chip having an ESDprotection device according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] The following detailed description of the embodiments refers tothe accompanying drawings which form a part hereof, and in which isshown by way of illustration specific embodiments in which theinventions may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical or mechanical changes may be madewithout departing from the scope of the present invention. The termswafer and substrate used in the following description include any basesemiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of a silicon supported by a basesemiconductor structure, as well as other semiconductor structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been used to form wells/junctions in the basesemiconductor structure, and terms wafer or substrate include theunderlying layers containing such wells/junctions. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

[0023]FIG. 1 is a prior art thin-oxide NPN ESD protection device. Device100 includes a p-type substrate 102 having an n-type source and drainregions 104 and 106. A gate 108 is separated from the substrate by athin layer of gate oxide 110. Gate 108 and source region 104 isconnected to a ground at node 112. Drain region 106 is connected to anexternal bonding pad 114. In a normal condition, device 100 is notconductive. During an ESD event, a high voltage occurs at externalbonding pad 114. When the voltage reaches a breakdown voltage level of ap-n junction (substrate/drain junction) of device 100, the devicebecomes conductive. A large amount of current starts to flow betweensource and drain regions 104 and 106. The current flow effectivelyreduces the high voltage at external bonding pad 114 thus protecting anyinternal circuit connected to external bonding pad 114.

[0024] One problem associated with device 100 of FIGS. 1 involves theintegrity of the gate oxide. The gate oxide can be put under atremendous stress or even be ruptured during an ESD event. In device100, a high electric field developed (due to high voltage at pad 114) atthe region underneath gate oxide 110 near the edge of drain 106 canrupture gate oxide 110. The high electric field can be reduced byconnecting a resistor between node 112 and gate 108. However, the devicestill suffers from other factors. During the ESD event, a hightemperature at the gate-drain edge is generated by the power dissipationcreated by a large amount of current flowing from drain 106 to source104 during a snapback operation. The high temperature along with thehigh electrical field, can escalate the stress or cause damage to thegate oxide. Moreover, the high temperature can also melt the portion ofsubstrate 102 underneath gate oxide 110, near drain 106. Furthermore,device 100 is also susceptible to a leakage failure due to impactionization, a well-known phenomenon to those skilled in the art. Impactionization at the edge of drain 106 causes carriers (electrons or holes)to be trapped in gate oxide 110. These trapped carriers cause a leakagepath between drain 106 and substrate 102 and eventually contribute toundesirable performance or failure of the device.

[0025]FIG. 2A is a prior art field-oxide NPN ESD protection device. Inthe Figure, device 200 includes a p-type substrate 202 having an n-typesource and drain regions 204 and 206 which are separated by an isolationstructure 208. Source region 204 is connected to a ground. Drain region206 is connected to an external bonding pad 210. In a normal condition,device 200 is not conductive. During an ESD event, a high voltage occursat external bonding pad 210. When the voltage reaches a breakdownvoltage level of the p-n junction (substrate/drain junction) of device200, the device becomes conductive. A large amount of current starts toflow between source and drain regions 204 and 206. The current floweffectively reduces the high voltage at external bonding pad 210, thus,protecting any internal circuit connected to external bonding pad 210.

[0026]FIG. 2B is another prior art field-oxide NPN ESD protectiondevice. In the Figure, device 220 includes a p-type substrate 222 havingan n-type source and drain regions 224 and 226 which are separated by anisolation structure 228. Source region 224 is connected to a ground.Drain region 226 is connected to an external bonding pad 230. In anormal condition, device 220 is not conductive. During an ESD event, ahigh voltage occurs at external bonding pad 230. When the voltagereaches a breakdown voltage level of the p-n junction (substrate/drainjunction) of device 220, the device becomes conductive. A large amountof current starts to flow between source and drain region 224 and 226.The current flow effectively reduces the high voltage at externalbonding pad 230 thus protecting any internal circuit connected toexternal bonding pad 230.

[0027] One problem associated with device 220 of FIG. 2B, includes areduction of the feedback efficiency of the device. Referring to FIG.2B, when device 220 is conductive, current flows from source 224 todrain 226. Since isolation structure 228 is positioned between thesource and drain, current has to flow down from source 224, aroundstructure 228, and then up to drain 226. Thus the current path islonger, and the direction is changed along the path. These two factorsreduce the efficiency of the flow of the current resulting in anincrease in snapback voltage. The increase in snapback voltage mayrequire a larger device size so that the pad voltage during the ESDevent does not increase because the increase in pad voltage could causedamage to the internal circuitry of the IC. However, a larger devicesize has its disadvantages. It increases total area of the IC. It alsoincreases input capacitance. In addition, the increase in snapbackvoltage also causes an increase in power dissipation. The increase inpower dissipation can cause stress to the device leading to substandardperformance. It can also cause damage to the device leading to failureto protect the internal circuity of the IC.

[0028]FIG. 3 is a novel ESD protection device according to theinvention. Device 300 includes a substrate 302 having a first doped(source) region 304 and a second doped (drain) region 306. First dopedregion 304 and second doped region 306 are separated by only a region311 of substrate 302. In one embodiment, substrate 302 has a p-typeconductivity material, and first and second doped regions 304 and 306have an n-type conductivity material. First and second doped regions 304and 306 have a higher doping concentration than the doping concentrationof substrate 302. In other words, substrate 302 is lightly doped(indicated by p−) and first and second doped regions 304 and 306 areheavily doped (indicated by n+). In addition, first doped region 304 canbe connected to a ground at node 312. Those of ordinary skill in the artcan readily recognize that first doped region 304 can also be connectedto a voltage source or a power source. Second doped region 306 can beconnected to an external bonding pad 312. Furthermore, since device 300of FIG. 3 includes no gate structure above the first and second dopedregions 304 and 306, it is a gateless ESD protection device.

[0029] Device 300 further comprises a first isolation structure 308 anda second isolation structure 310. First isolation structure 308 isplaced on an opposing side, side 313, of the first doped region fromsubstrate region 311. Second isolation structure 310 is placed on anopposing side, side 315, of the second doped region from substrateregion 311. The isolation structures are designed to isolate device 300from other adjacent components within the IC.

[0030] As shown in FIG. 3, device 300 has no gate oxide. Since device300 has no gate oxide, it does not suffer from gate oxide ruptureproblem and leakage failure as in the case of a thin-oxide device. Thus,this is one advantage of device 300 of the invention over the prior artdevice 100 shown in FIG. 1. Device 300 also has no isolation structurepositioned between source region 304 and drain region 306. Thus, currentcan travel in a shorter path and directly from source region 304 todrain region 306 and without changing direction. Therefore, the issue ofhigh snapback voltage, as in the case of a field-oxide device 220, isavoided. In addition, since device 300 includes no gates structure, whenit conducts, an amount of current flowing between the first and seconddoped regions 304 and 306 is not controlled by a voltage potential of agate above the first and second doped regions.

[0031]FIG. 4 illustrates a p-n junction of ESD protection device 300 ofFIG. 3. In the Figure, p-n junction 400 depicts the junction betweenp-type substrate 302 and n-type second doped region 306 when areverse-bias voltage is applied to external bonding pad 312. In FIG. 4,p-n junction 400 includes a center 402 and a space charge region 404.The space charge region exists due to the difference in conductivitytypes of (p-type) substrate 302 and the (n-type) first and second dopedregions 304 and 306. Space charge region 404 has a first boundary 406 aand a second boundary 408. The first and second boundaries 406 a and 408a are not symmetrical with reference to center 402. As shown in FIG. 4,from center 402, first boundary 406 a extends more into substrate 302because second doped region 306 is heavily doped and substrate 302 islightly doped. In an alternate embodiment, those of ordinary skill inthe art will readily recognize that substrate 302 and first and seconddoped regions 304 and 306 can have the same doping concentration. Inthat case, first and second boundaries 406 a and 408 a willsymmetrically extend from the center.

[0032] When the reverse-bias voltage at external bonding pad 312increases, space charge region 404 expands predominantly into substrate302. As shown in FIG. 4, first boundary 406 a expands to a positionindicated at 406 b, and second boundary 408 a expands to a positionindicated at 408 b. As the reverse-bias voltage at external bonding pad312 increases, the width of space charge region 404 becomes wider. Whenthe reverse-bias voltage reaches a voltage level known as reverse-biasbreakdown voltage or breakover voltage (Vbv), current begins to flowbetween second doped region 306 and the substrate 302, which is theinitiation of the negative resistance region leading to snapbackconduction between the doped region 306 and 304. Snapback conduction isnot described herein as it is a phenomenon known to those of ordinaryskill in the art.

[0033]FIG. 5 illustrates a current vs. voltage graph of the ESDprotection device of FIG. 3 operating in a snapback mode. As shown inFIG. 5, when a reverse-bias voltage at external bonding pad 312 is lessthan the breakover voltage (Vbv), there is little or an insignificantamount of current flowing. As indicated in the graph, at region 502 thecurrent is near zero. When the reverse-bias voltage reaches thebreakover voltage (Vbv) as shown at point 504, device 300 starts tooperate in a snapback mode and pulls the voltage at external bonding pad312 to a snapback voltage (Vsb) as shown at region 506. The currentflows with low impedance in the snapback mode, as indicated by line 508with a steep slope. The steep slope also indicates that the device has alow resistance between the first and second doped regions during thesnapback mode. The flow of current effectively lowers the voltage atexternal bonding pad 312 to a safe level while conducting largecurrents.

[0034] FIGS. 6A-C illustrate cross-sectional views of an ESD protectiondevice 600, at various processing stages according to one embodimentaccording to the invention. FIG. 6A shows a substrate 601. An implantprocess introduces p-type dopants into the substrate. In one embodiment,introducing p-type dopants forms a lightly doped substrate (p-) 601. InFIG. 6B, a resist 602 masks substrate 601 to expose a first and secondexposed areas 603 and 605 which define future doped regions. An implantprocess introduces n-type dopants to the exposed areas 603 and 605. Inone embodiment, introducing n-type dopants forms heavily doped first andsecond regions 604 and 606. In FIG. 6C, after the resist is removed,device 600 has been formed which includes a first active region or ann-type first doped region 604, and a second active region or an n-typesecond doped region 606 separated by a portion of the p-type substrate601. Furthermore, the space separating the first and second dopedregions 604 and 606 is defined by the length of resist 602.

[0035] FIGS. 7A-E illustrate cross-sectional views of an ESD protectiondevice 700, at various processing stages according to another embodimentof the invention. In FIG. 7A, an implant process introduces p-typedopants into a substrate 701. In one embodiment, introducing p-typedopants forms a lightly doped substrate (p−) 701. In FIG. 7B, a resist702 masks substrate 701 to expose a first and second exposed areas 703and 705 which define future doped regions. A first implant processintroduces p-type dopants into the exposed areas to form a first and asecond p-type (p-type halo) doped regions 724 and 726. After that, asecond implant introduces n-type dopants into the exposed areas to forma first and second n-type lightly doped (LDD) regions 714 and 716.

[0036] In FIG. 7C, resist 702 is removed, and another resist 703 maskssubstrate 701 to expose areas 707 and 709. In FIG. 7D, a third implantprocess introduces n-type dopants to the exposed areas to form a first(source) and second (drain) n-type heavily doped regions 704 and 706(n+). In FIG. 7E resist 703 is removed to complete device 700. Device700 includes two active regions 734 and 736. Each of the active regionsincludes a source/drain region 704 or 706, an LDD region 714 or 716 anda halo region 724 or 726. As shown in FIG. 7E, the source/drain, LDD andhalo regions have different depths. Halo regions 724 and 726 have afirst depth. LDD regions 714 and 716 have a second depth, which isshallower than the first depth. And source and drain region 704 and 706have a third depth which is shallower than the second depth.

[0037] FIGS. 8A-E illustrate cross-sectional views of an ESD protectiondevice 800, at various processing stages according to another embodimentaccording to the invention. In FIG. 8A, an implant process introducesp-type dopants into a substrate 801. In one embodiment, introducingp-type dopants forms a lightly doped substrate (p) 801. In FIG. 8B, aresist 802 masks substrate 801 to expose an exposed area 803 whichdefine future doped region. A first implant process introduces p-typedopants into the exposed area to form a p-type (p-type halo) dopedregions 824. After that, a second implant introduces n-type dopants intothe exposed area to form an n-type lightly doped (LDD) regions 814.

[0038] In FIG. 8C, resist 802 is removed, and another resist 803 maskssubstrate 801 to expose exposed areas 807 and 809. In FIG. 8D, a thirdimplant process introduces n-type dopants to the exposed areas to form afirst (source) and second (drain) n-type heavily doped regions 804 and806 (n+). In FIG. 8E resist 803 is removed and device 800 has beenformed. Device 800 includes first and second active regions 834 and 836,each of which includes a source/drain region 804 or 806. First region804 further includes LDD region 814 and halo region 824. Halo region 824surrounds LDD region 814, which in turn, surrounds source/drain region804.

[0039] FIGS. 9A-E illustrate cross-sectional views of an ESD protectiondevice 900, at various processing stages according to another embodimentaccording to the invention. In FIG. 9A, a substrate 901 is provided. Inone embodiment, introducing p-type dopants forms a lightly dopedsubstrate (p−) 901. In FIG. 9B, a resist 902 masks substrate 901 toexpose an area 903. A first implant process introduces p-type dopantsinto the exposed area to form a p-type (p-type halo) doped regions 924.After that, a second implant introduces n-type dopants into the exposedarea to form an n-type lightly doped (LDD) regions 914.

[0040] In FIG. 9C, resist 902 is removed. Another resist 903 maskssubstrate 901 and regions 914 and 924 to expose areas 907 and 909. InFIG. 9D, a third implant process introduces n-type dopants to exposedareas 903 and 905 to form a source/drain region 906 and an ohmic-contactregion 904. Regions 906 and 904 have a higher doping concentration thana doping concentration of n-type LDD region 914. In FIG. 9E resist 903is removed to form device 900. Device 900 includes first and secondactive regions 934 and 936. First active region 934 includes LDD region914, halo region 924 surrounding LDD region 914, and ohmic-contactregion 904 adjacent to halo region 924. Second active region 936 includesource/drain region 906.

[0041] The halo and LDD regions described in the processes of formingdevices 700, 800 and 900 provide one advantage. They allow a shorter andmore stable device, which provides lower impedance. However, forming thehalo and LDD regions introduces the misalignment between the mask steps.

[0042] The processes described above regarding devices 600, 700, 800 and900 are not exclusive. Other processes or steps can be used to achievethe same purpose. In some embodiments, more mask steps can be usedbetween implants, or multiple implants can be introduced and some ofwhich may be grouped into common mask step. For example, in oneembodiment, an additional mask can be used between the halo and the LDDimplants. In another embodiment, more or less implants other than thehalo, LDD and source/drain can be introduced, and they can be groupedinto common mask step.

[0043] In addition, other variations of devices 600, 700, 800 and 900described above can readily achieve the same advantages provided bydevices 600-900 of the invention. For example, in one other embodiment,a device similar to any of the devices 600-900 includes the halo and LDDimplants on both sides without a source/drain implant on either side. Insuch embodiment, a source/drain implant can be introduced in animmediate proximity of the halo and LDD implants to provide the ohmiccontacts. In yet another embodiment, a device similar to any of thedevices 600-900 includes the halo and LDD implants on both sides, andeither the source or the drain is included in only one side.

[0044]FIG. 10 is a block diagram of an integrated circuit 1000 having anESD protection device according to the invention. Integrated circuit1000 includes an external bonding pad 1002 connected to an internalcircuit 1004 at node 1006. A first ESD protection device 1008 isconnected between node 1006 and a first voltage source 1007. A secondESD protection device 1010 is connected between node 1006 and a secondvoltage source 1009. ESD protection devices 1008 or 1010 represents theESD protection devices 300, 600, 700, 800 or 900 according to theinvention. The first voltage source is substantially greater than thesecond voltage source. For example, the first voltage source can be avoltage supply (or the operating voltage of the device) and the secondvoltage source can be a ground.

[0045] In a normal condition, ESD protection devices 1008 and 1010 donot conduct. During an ESD event, a high voltage occurs at bonding pad1002. When the voltage reaches the breakover voltage of the ESDprotection devices 1008 and 1010, the devices begin to conduct and pullthe voltage at external bonding pad 1002 back to the level of thesnapback voltage and operate in a snapback mode. By operating in thesnapback mode, the voltage at node 1006 remains close to the level ofthe snapback voltage. Therefore, according to the teaching of theinvention, internal circuit 1004 is protected by the ESD protectiondevices from the ESD event.

[0046]FIG. 11 is a block diagram of a semiconductor chip having an ESDprotection device according to the invention. In the Figure, chip 1100includes a package 1102 having plurality of pins 1104. As shown in apartially cut-away view, at least one of the pins of the package isconnected to at least one ESD protection device 1106 of the presentinvention at a node 1108. Device 1104 protects the chip from an ESDevent and can be any of the ESD protection devices according to theinvention, such as device 300, 600, 700, 800 or 900.

Conclusion

[0047] A novel ESD protection device is provided which overcomes theproblems and limitations of the prior art ESD protection devices. TheESD protection device according to the invention is less susceptible tofailures seen in the present NPN snapback ESD protection devices.

[0048] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is intended that this invention be limited onlyby the claims and the equivalents thereof.

What is claimed is:
 1. A method of producing a semiconductor device, themethod comprising: masking a substrate with a resist, the substratehaving no gate structure over the substrate; and forming a first doperegion and a second doped region in the substrate, wherein the first andsecond doped regions are separated by only the substrate, wherein aspacing between the first and second doped regions is defined by alength of the resist between the first and second doped regions, whereinthe method includes forming no gate above the substrate.
 2. The methodof claim 1, wherein: the first and second doped regions have a firstconductivity type; and the substrate has a second conductivity typedifferent from the first conductivity type.
 3. The method of claim 1further comprising: forming a third doped region within the first dopedregion; and forming a fourth doped region within the second dopedregion.
 4. The method of claim 3, wherein: the first and second dopedregions have a first conductivity type; and the third and fourth dopedregions have a second conductivity type different from the firstconductivity type.
 5. The method of claim 4, wherein first and seconddoped regions have a higher doping concentration than the third andfourth doped regions.
 6. The method of claim 4 further comprising:forming a fifth doped region within the third source/drain region; andforming sixth doped region within the fourth doped region.
 7. The methodof claim 6, wherein: the fifth and sixth doped regions have a firstconductivity type; and the first and second doped regions have a secondconductivity type different from the first conductivity type.
 8. Amethod of producing a semiconductor device, the method comprising:providing a substrate having no gate structure over the substrate;masking a substrate with a resist having openings for forming a firstunmasked region and a second unmasked region of the substrate, whereinthe unmasked regions are separated by a length of the resist between theunmasked regions; implanting dopants into the first and second unmaskedregions to form a first source/drain region and a second source/drainregions; and removing the resist, wherein the method includes forming nogate above the substrate.
 9. The method of claim 8, wherein: the firstand second source/drain regions have a first conductivity type; and thesubstrate has a second conductivity type different from the firstconductivity type.
 10. The method of claim 8 further comprising: forminga first halo region surrounding the first source/drain region; andforming second halo region surrounding the second source/drain region.11. The method of claim 10 further comprising: forming a first lightlydoped region within the first source/drain region; and forming secondlightly doped region within the second source/drain region.
 12. Themethod of claim 11, wherein: the first and second lightly doped regionsand the first and second source/drain regions have a first conductivitytype. the substrate and the first and second halo regions have a secondconductivity type different from the first conductivity type.
 13. Themethod of claim 11, wherein first and second source/drain regions have ahigher doping concentration than the lightly doped regions.
 14. A methodof producing a semiconductor device, the method comprising: providing asubstrate having no gate structure over the substrate; masking thesubstrate with a resist to define a first unmasked region and secondunmasked region, the first and second unmasked regions being separatedby a distance equaled to a length of a the resist between the first andsecond unmasked regions; implanting dopants into the first and secondunmasked regions to form a first source/drain region; and removing theresist, wherein the method includes forming no gate above the substrate.15. The method of claim 14, wherein: the first and second source/drainregions have a first conductivity type; and the substrate has a secondconductivity type different from the first conductivity type.
 16. Themethod of claim 14 further comprising: forming a first halo regionsurrounding the first source/drain region; and forming second haloregion surrounding the second source/drain region.
 17. The method ofclaim 16 further comprising: forming a first lightly doped region withinthe first source/drain region; and forming second lightly doped regionwithin the second source/drain region.
 18. The method of claim 17,wherein: the first and second lightly doped regions and the first andsecond source/drain regions have a first conductivity type. thesubstrate and the first and second halo regions have a secondconductivity type different from the first conductivity type.
 19. Themethod of claim 17, wherein first and second source/drain regions have ahigher doping concentration than the lightly doped regions.
 20. A methodof making a semiconductor, the method comprising: providing a substratehaving no gate structure formed above the substrate; forming a firsthalo region and a second halo region in the substrate; forming a firstlightly doped region within the first halo region; forming a secondlightly doped region within the second halo region; forming a firstsource/drain region within the first lightly doped region; and forming asecond source/drain region within the second lightly doped regionwithout forming a gate over the substrate, wherein the method includesforming no gate above the substrate.
 21. The method of claim 20,wherein: the first and second source/drain regions have a firstconductivity type; and the substrate has a second conductivity typedifferent from the first conductivity type.
 22. The method of claim 21,wherein: the first and second source/drain regions have an n-typematerial; and the substrate has a p-type material.
 23. The method ofclaim 20, wherein: the first and second lightly doped regions and thefirst and second source/drain regions have a first conductivity type,and the substrate and the first and second halo regions have a secondconductivity type different from the first conductivity type.
 24. Themethod of claim 20, wherein first and second source/drain regions have ahigher doping concentration than the first and second lightly dopedregions.
 25. The method of claim 20, wherein first and secondsource/drain regions have a higher doping concentration than thesubstrate.
 26. A method of making a semiconductor, the methodcomprising: providing a substrate having no gate structure formed abovethe substrate; masking the substrate with a resist, the resist havingopenings for exposing a first exposed area and a second exposed area ofthe substrate; forming a first halo region in the first exposed area,and forming a second halo region in the second exposed area; forming afirst lightly doped region within the first halo region; forming asecond lightly doped region within the second halo region; forming afirst source/drain region within the first lightly doped region; andforming a second source/drain region within the second lightly dopedregion, wherein the method includes forming no gate above the substrate.27. The method of claim 26, wherein first and second source/drainregions have a higher doping concentration than the first and secondlightly doped regions.
 28. The method of claim 26, wherein first andsecond source/drain regions have a higher doping concentration than thesubstrate.
 29. The method of claim 26, wherein: the substrate and thefirst and second halo regions have a first conductivity type; and thefirst and second lightly doped regions and the first and secondsource/drain regions have a second conductivity type different from thefirst conductivity type.
 30. The method of claim 29, wherein: thesubstrate and the first and second halo regions have a p-type material;and the first and second lightly doped regions and the first and secondsource/drain regions have an n-type material.
 31. The method of claim 26further comprising: removing the resist after forming the first andsecond halo regions; and masking the substrate with a second resistbefore forming the first and second lightly doped regions, the secondresist having openings for exposing the first and second halo regions.32. The method of claim 31 further comprising: removing the secondresist after forming the first and second lightly doped regions; andmasking the substrate with a third resist before forming the first andsecond source/drain regions, the third resist having openings forexposing the lightly doped regions.
 33. The method of claim 26 furthercomprising: removing the resist after forming the first and secondlightly doped regions; and masking the substrate with a second resistbefore forming the first and second source/drain regions, the secondresist having openings for exposing the lightly doped regions.
 34. Amethod of making a semiconductor, the method comprising: providing asubstrate having no gate structure formed above the substrate; maskingthe substrate with a first resist, the first resist having a firstopening and a second opening for exposing a first exposed area and asecond exposed area of the substrate; and implanting dopant into thefirst exposed area to form a first halo region, and implanting dopantinto the second exposed area to form a second halo region, wherein thefirst and second halo regions are separated by a portion of thesubstrate having a length equal to a length between the first and thesecond openings of the first resist; removing the first resist; maskingthe substrate with a second resist, the second resist having a firstopening and a second opening for exposing the first and second haloregions; forming a first lightly doped region within the first haloregion, and forming a second lightly within the second halo region;forming a first source/drain region within the first lightly dopedregion; and forming a second source/drain region within the secondlightly doped region, wherein the method includes forming no gate abovethe substrate.
 35. The method of claim 34, wherein first and secondsource/drain regions have a higher doping concentration than the firstand second lightly doped regions.
 36. The method of claim 34, whereinfirst and second source/drain regions have a higher doping concentrationthan the substrate.
 37. The method of claim 34, wherein: the substrateand the first and second halo regions have a first conductivity type;and the first and second lightly doped regions and the first and secondsource/drain regions have a second conductivity type different from thefirst conductivity type.
 38. The method of claim 37, wherein: thesubstrate and the first and second halo regions have a p-type material;and the first and second lightly doped regions and the first and secondsource/drain regions have an n-type material.
 39. A method of making asemiconductor, the method comprising: providing a substrate having nogate structure formed above the substrate; masking the substrate with afirst resist, the first resist having a first opening and a secondopening for exposing a first exposed area and a second exposed area ofthe substrate; implanting dopant into the first exposed area to form afirst halo region, and implanting dopant into the second exposed area toform a second halo region, wherein the first and second halo regions areseparated by a portion of the substrate having a length equal to alength between the first and the second openings of the first resist;removing the first resist; masking the substrate with a second resist,the second resist having a first opening and a second opening forexposing the first and second halo regions; forming a first lightlydoped region within the first halo region, and forming a second lightlywithin the second halo region, wherein the first and second lightlydoped regions are separated by distance equal to a length between thefirst and the second openings of the second resist; removing the secondresist; masking the substrate with a third resist, the third resisthaving a first opening and a second opening for exposing the first andsecond lightly doped regions; and forming a first source/drain regionwithin the first lightly doped region, and forming a second source/drainregion within the second lightly doped region, wherein the methodincludes forming no gate above the substrate.
 40. The method of claim39, wherein first and second source/drain regions have a higher dopingconcentration than the first and second lightly doped regions.
 41. Themethod of claim 39, wherein first and second source/drain regions have ahigher doping concentration than the substrate.
 42. The method of claim39, wherein: the substrate and the first and second halo regions have afirst conductivity type; and the first and second lightly doped regionsand the first and second source/drain regions have a second conductivitytype different from the first conductivity type.
 43. The method of claim42, wherein: the substrate and the first and second halo regions have ap-type material; and the first and second lightly doped regions and thefirst and second source/drain regions have an n-type material.
 44. Amethod of making a semiconductor, the method comprising: providing asubstrate having no gate structure formed above the substrate; maskingthe substrate with a first resist, the first resist having an openingfor exposing an exposed area the substrate; forming a halo region and alightly doped region in the exposed area; removing the first resist;masking the substrate with a second resist, the second resist having afirst opening for exposing the halo and the doped regions, and a secondopening for exposing a second exposed area of the substrate; and forminga first source/drain region within the lightly doped region, and forminga second source/drain region in the second exposed area of thesubstrate, wherein the method includes forming no gate above thesubstrate.
 45. The method of claim 44, wherein first and secondsource/drain regions have a higher doping concentration than the lightlydoped region.
 46. The method of claim 44, wherein first and secondsource/drain regions have a higher doping concentration than thesubstrate.
 47. The method of claim 44, wherein: the substrate and thehalo region have a first conductivity type; and the lightly doped regionand the first and second source/drain regions have a second conductivitytype different from the first conductivity type.
 48. The method of claim47, wherein: the substrate and the halo region have a p-type material;and the lightly doped region and the first and second source/drainregions have an n-type material.
 49. A method of making a semiconductor,the method comprising: providing a substrate having no gate structureformed above the substrate; masking the substrate with a first resist,the first resist having an opening for exposing an exposed area thesubstrate; forming a halo region and a lightly doped region in theexposed area; removing the first resist; masking the substrate with asecond resist, the second resist having a first opening for exposing asecond exposed area of the substrate, and a second opening for exposinga third exposed area of the substrate, and forming a first source/drainregion in the second exposed area, and forming a second source/drainregion in the third exposed area, wherein the method includes forming nogate above the substrate.
 50. The method of claim 49, wherein masking asecond resist include masking the halo and lightly doped regions. 51.The method of claim 49, wherein the first source/drain region isadjacent to the halo region.
 52. The method of claim 49, wherein firstand second source/drain regions have a higher doping concentration thanthe lightly doped region.
 53. The method of claim 49, wherein first andsecond source/drain regions have a higher doping concentration than thesubstrate.
 54. The method of claim 49, wherein: the substrate and thehalo region have a first conductivity type; and the lightly doped regionand the first and second source/drain regions have a second conductivitytype different from the first conductivity type.
 55. The method of claim54, wherein: the substrate and the halo region have a p-type material;and the lightly doped region and the first and second source/drainregions have an n-type material.